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1) Arithmetic Logic Unit: "The part of the CPU where data is processed and manipulated. This processing and manipulation normally consists of arithmetic operations or logical comparisons allowing a program to make decisions." a) ALU b) MAR c) Address Bus d) CU 2) Control Unit: “The part of the CPU that manages the execution of instructions. The control unit fetches each instruction in sequence, and decodes and synchronises it before executing it by sending control signals to other parts of the computer.” a) Cache b) Cores c) CU d) Clock Speed 3) “Tiny areas of extremely fast memory located in the CPU normally designed for a specific purpose, where data or control information is stored temporarily.” a) Pipelining b) Cores c) Fetch-Decode-Execute d) Register 4) Program Counter: “A register in the control unit which holds the address of the next instruction to be executed.” a) PC b) Register c) CIR d) Data Bus 5) Accumulator: “A special register within the ALU. It is used to hold the data currently being processed by the central processor. Any data to be processed is stored temporarily in the accumulator, the results ending up back in the accumulator being stored in the memory unit.” a) MAR b) ALU c) ACC d) Clock Speed 6) Memory Address Register: “A register in the CPU that stores the address of the memory location currently in use. In the fetch phase, this would be the address of the instruction being loaded; in the execute phase, it would be the address of the data being used.” a) MAR b) Cache c) ACC d) Pipelining 7) Memory Data Register: “A register in the CPU that stores data being transferred to and from the immediate-access store. It acts as a buffer, allowing the central processor and memory unit to act independently without being affected by minor differences in operation. A data item will be copied to the MDR ready for use at the next clock pulse, when it can either be used by the central processor or be stored in main memory.” a) MDR b) Cache c) Clock Speed d) Fetch-Decode-Execute 8) Current Instruction Register: “A register in the control unit that stores the address of the next instruction currently being executed and decoded.” a) Data Bus b) Clock Speed c) CIR d) ALU 9) “A common physical pathway shared by signals to and from several components of a computer.” a) Register b) Busses c) Data Bus d) Cache 10) “The part of the bus which carries the actual information.” a) Data Bus b) CPU c) CU d) MDR 11) “The part of the bus which carries identification about where the data is being sent.” a) Address Bus b) Register c) CIR d) MDR 12) “This bus carries command and control signals to and from every other component of a computer.” a) Control Bus b) CU c) Data Bus d) CPU 13) “The complete process of retrieving an instruction from store, decoding it and carrying it out. Also known as the instruction cycle.” a) Fetch-Decode-Execute b) MAR c) Control Bus d) Busses 14) Central Processing Unit: “The main part of the computer, consisting of the registers, ALU and control unit.” a) Clock Speed b) Data Bus c) Busses d) CPU 15) “Measured in Hertz, the clock speed is the frequency at which the internal clock generates pulses. The higher the clock rate, the faster the computer may work. The “clock” is the electronic unit that synchronises related components by generating pulses at a constant rate.” a) Control Bus b) CU c) PC d) Clock Speed 16) “A part of a multi-core processor. A multi-core processor is a single component with two or more independent actual CPUs, which are the units responsible for the fetch-decode-execute cycle.” a) Data Bus b) ACC c) Cores d) CU 17) “A part of the main store between the central processor and the rest of the memory. It has extremely fast access, so sections of a program and its associated data are copied there to take advantage of its short fetch cycle.” a) MAR b) CPU c) Cache d) Address Bus 18) “Successive steps of an instruction sequence are executed in turn by a sequence of cores able to operate concurrently, so that another instruction can be begun before the previous one is finished.” a) Pipelining b) Cache c) Cores d) ALU

Structure and Function of the Processor (A-Level)

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